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AS3693A QFN48
austria micro systems
Figure 4 – I C Sequential-Read:
the transmitter. In this state the slave transmits register data located by the previous received word address
vector. The master responds to the data byte with a not-acknowledge, and issues a STOP condition on the bus.
2
S
DW
A
WA
A Sr
DR
A
data 1
A
data 2
…
A
data n
N P
read register
WA++
Figure 5 – I C Current-Address-Read:
WA++
Sequential-Read is the extended form of Random-Read, as more than one register-data bytes are transferred
subsequently. In difference to the Random-Read, for a sequential read the transferred register-data bytes are
responded by an acknowledge from the master. The number of data bytes transferred in one sequence is
unlimited (consider the behavior of the word-address counter). To terminate the transmission the master has to
send a not-acknowledge following the last data byte and generate the STOP condition subsequently.
2
S
DR
A
data 1
A
data 2
…
A
data n
N P
read register
WA++
read register
WA++
read register
WA++
WA++
1 register byte. Analogous to Sequential-Read an unlimited number of data bytes can be transferred, where the
To keep the access time as small as possible, this format allows a read access without the word address transfer
in advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-
Read address. Analogous to Random-Read, a single byte transfer is terminated with a not-acknowledge after the
st
data bytes has to be responded with an acknowledge from the master. For termination of the transmission the
master sends a not-acknowledge following the last data byte and a subsequent STOP condition.
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